The embodiments presented herein relate to integrated circuits and, more particularly, to configurable storage blocks in an integrated circuit.
As applications for which programmable integrated circuits are used increase in complexity, it has become more common to design programmable integrated circuits to include specialized blocks such as configurable storage blocks in addition to blocks of generic programmable logic.
Configurable storage blocks are often arranged in arrays of memory elements. In a typical array, data lines are used to write data into and read data from the configurable storage blocks. Address lines may be used to select which of the memory elements are being accessed. A configurable storage block is typically configurable to implement a memory of a given depth and width, whereby the maximum depth is based on the number of address lanes and the maximum width on the number of data lanes.
Furthermore, programmable integrated circuits often include simple registers without an input for enable signals. Errors can occur if simple registers are continuously enabled to output data without pause, even when downstream circuitry is not ready to receive the output data.
It is within this context that the embodiments herein arise.